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Verification Methodology Manual for SystemVerilog

Jezik EngleskiEngleski
Knjiga Meki uvez
Knjiga Verification Methodology Manual for SystemVerilog Hunter
Libristo kod: 09165363
Nakladnici Springer-Verlag New York Inc., prosinac 2014
Offers users the first resource guide that combines both the methodology and basics of SystemVerilog... Cijeli opis
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Offers users the first resource guide that combines both the methodology and basics of SystemVerilog§§Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.§§Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.§

Informacije o knjizi

Puni naziv Verification Methodology Manual for SystemVerilog
Autor Hunter, Alan (North Carolina State University, University of Leeds North Carolina State Univ. North Carolina State Univ. North Carolina State Univ. No
Jezik Engleski
Uvez Knjiga - Meki uvez
Datum izdanja 2014
Broj stranica 503
EAN 9781461498131
ISBN 9781461498131
Libristo kod 09165363
Nakladnici Springer-Verlag New York Inc.
Težina 795
Dimenzije 155 x 28 x 29

Kategorija

Technology, Engineering, Agriculture > Electronics & communications engineering > Electronics engineering > Electronics: circuits & components
Technology, Engineering, Agriculture > Technology: general issues > Engineering: general
Technology, Engineering, Agriculture > Energy technology & engineering > Electrical engineering
Computing & Information Technology > Graphical & digital media applications > Computer-aided design (CAD)
Computing & Information Technology > Computer programming / software engineering > Compilers & interpreters
Computing & Information Technology > Computer programming / software engineering > Programming & scripting languages: general
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