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RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

Jezik EngleskiEngleski
Knjiga Meki uvez
Knjiga RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design Stuart Sutherland
Libristo kod: 18580422
Nakladnici Createspace Independent Publishing Platform, lipanj 2017
This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Descri... Cijeli opis
? points 292 b
116.12 €
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This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synt

Informacije o knjizi

Puni naziv RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Autor Stuart Sutherland
Jezik Engleski
Uvez Knjiga - Meki uvez
Datum izdanja 2017
Broj stranica 488
EAN 9781546776345
ISBN 1546776346
Libristo kod 18580422
Nakladnici Createspace Independent Publishing Platform
Težina 643
Dimenzije 152 x 229 x 25

Kategorija

Technology, Engineering, Agriculture > Electronics & communications engineering > Electronics engineering
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