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Logic Design and Verification Using SystemVerilog (Revised)

Jezik EngleskiEngleski
Knjiga Meki uvez
Knjiga Logic Design and Verification Using SystemVerilog (Revised) Donald Thomas
Libristo kod: 17581064
Nakladnici Createspace Independent Publishing Platform, ožujak 2016
SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels... Cijeli opis
? points 172 b
68.40 €
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SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The ma

Informacije o knjizi

Puni naziv Logic Design and Verification Using SystemVerilog (Revised)
Autor Donald Thomas
Jezik Engleski
Uvez Knjiga - Meki uvez
Datum izdanja 2016
Broj stranica 336
EAN 9781523364022
ISBN 1523364025
Libristo kod 17581064
Nakladnici Createspace Independent Publishing Platform
Težina 598
Dimenzije 189 x 246 x 18

Kategorija

Computing & Information Technology > Computer science > Computer architecture & logic design
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