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Formal Semantics and Proof Techniques for Optimizing VHDL Models

Jezik EngleskiEngleski
Knjiga Meki uvez
Knjiga Formal Semantics and Proof Techniques for Optimizing VHDL Models Kothanda Umamageswaran
Libristo kod: 06796876
Nakladnici Springer-Verlag New York Inc., studeni 1998
Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifyi... Cijeli opis
? points 304 b
121.31 €
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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Informacije o knjizi

Puni naziv Formal Semantics and Proof Techniques for Optimizing VHDL Models
Autor Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
Jezik Engleski
Uvez Knjiga - Meki uvez
Datum izdanja 1998
Broj stranica 158
EAN 9781461373315
ISBN 146137331X
Libristo kod 06796876
Nakladnici Springer-Verlag New York Inc.
Težina 290
Dimenzije 155 x 235 x 11

Kategorija

Technology, Engineering, Agriculture > Electronics & communications engineering > Electronics engineering > Electronics: circuits & components
Technology, Engineering, Agriculture > Energy technology & engineering > Electrical engineering
Computing & Information Technology > Graphical & digital media applications > Computer-aided design (CAD)
Computing & Information Technology > Computer programming / software engineering > Programming & scripting languages: general
Mathematics & Science > Mathematics
Computing & Information Technology > Computer hardware
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